Methods that increase feature density on semiconductor devices within a shrinking footprint are constantly evolving to meet demands for smaller, more powerful electronic devices. However, in some examples, practical considerations may limit how far those methods may evolve. For example, FIG. 1 is an illustrative cross-section of a prior art example of a metal pattern formed on an underlying layer in 45 nm processes. As illustrated, in FIG. 1, metal 102 may be formed by well-known method into a pattern on an underlying layer 106. For example, metal 102 can be deposited and etched using standard photolithographic techniques. For clarity, only a portion of an example of the fine metal pattern is illustrated in cross-section. Metal patterns may form any number of features or connective lines. Insulator 104 may be provided to form a barrier between metal lines 108 and 110. Metal lines 108 and 110 may have a width 112 of approximately 45 nm and insulator 104 may have a width 114 of approximately 45 nm. As such, pitch 116 of the feature is approximately 90 nm.
In some conventional examples, in order to accommodate more densely arranged features, a decrease in pitch is generally required. With conventional methods of fabrication as described above, this would require moving to a more expensive means of fabrication. For example, a more expensive photolithography tool may be required. Thus, it would be desirable to develop methods that increase feature density without increasing the fabrication expense.
Furthermore, as the line width decreases, metal volume of conducting lines also decreases, thus resulting in an increase in resistance of conductive lines. Thus, it may be desirable to develop methods which provide for increased feature density without a commensurate decrease in conductor linewidth. For example, to fit wider conductor lines in the same area, it would be desirable to minimize the width of gaps between them.